1. Field of the Invention
This invention relates to integrated circuit devices and, in particular, to the clamping of signal voltages at the pins of integrated circuit devices.
2. Related Art
Advances in digital integrated circuit technology have resulted in devices that operate at increasingly high frequencies. One system-level by-product of such operation is an increased tendency for inter-chip signals to develop significant levels of distortion. This distortion includes numerous undesirable characteristics, e.g., signal undershoot, signal overshoot, signal ringing and signal reflection.
There are many potential sources of signal distortion in a modern digital system implementation. One significant source of signal distortion is impedance mismatch in a signal propagation path. Impedance mismatch gives rise to distortions commonly referred to as "transmission line effects." These effects, along with other signal distortions, tend to become more pronounced (and detrimental) as the operating frequency of the digital system increases. Current operating frequencies of digital systems approach 100-200 MHz. At this speed, board-level traces of approximately two or more inches may induce significant transmission line effects.
FIG. 1 illustrates both an "ideal" undistorted inter-chip signal voltage 100 and a "real" distorted inter-chip signal voltage 110 in a typical digital system. FIG. 1 is a graph of signal voltage versus time as the inter-chip signal transitions from a logic high voltage 121 to a logic low voltage 120 and back to a logic high voltage 121 again. The logic high voltage 121 and logic low voltage 120 levels are system design and technology dependent values that are typically known and fixed values for a given system implementation.
With respect to the ideal signal voltage 100, two points should be noted. First, the voltage 100 transitions between logic low voltage 120 and logic high voltage 121 infinitely fast. Second, at the end of a transition, the voltage 100 does not overshoot or undershoot the new voltage level, but rather stops precisely at that level.
In contrast to the ideal signal voltage 100, the voltage transitions for a real signal voltage 110 require a finite, non-zero amount of time. Transition times (10%-90%) of 1-3 nanoseconds are typical of current digital systems. Additionally, unlike the ideal signal voltage 100, the real signal voltage 110 exhibits signal distortions such as undershoot 111 when transitioning to logic low voltage 120, overshoot 112 when transitioning to logic high voltage 121, and ringing (i.e., damped oscillation about either the system logic high voltage 121 or system logic low voltage 120).
These signal distortions have created numerous problems for system designers. The problems include: device malfunction due to spurious input and/or output transitions, device latch-up (particularly in CMOS technology), and device violation of AC and/or DC parametric specification. Since the source of the undesirable signal distortions in digital systems is a function not only of the integrated circuit components, but also of "external" factors (e.g., printed circuit board design and layout, component drive requirements and associated loading, and system frequency), it is important for integrated circuit manufacturers to provide products with a high degree of tolerance and insensitivity to the previously described signal distortions.
Clamp circuits have been used on the input and output pins of integrated circuit devices for many years to minimize the creation and maintenance of the aforementioned signal distortions in digital systems. All prior art clamp circuits operate on the principle of providing a variable impedance for each device pin. Depending on the magnitude of the incoming voltage signal, the clamp circuit appears as either high impedance (an open circuit) or low impedance (a short circuit) to the incoming voltage signal.
FIG. 2A is a graph of clamp current versus pin voltage. The clamp current versus pin voltage characteristic 200 of an ideal clamp circuit is shown. When the pin voltage is between the system logic high voltage 202 and system logic low voltage 201, the clamp circuit operates as an open circuit and has no effect on the signal voltage present at the device pin (i.e., the clamp current is zero).
When the pin voltage either falls below the system logic low voltage 201 or rises above the system logic high voltage 202, the clamp circuit operates as a short circuit (i.e., switches from high impedance to low impedance) and sources any necessary current 203 or 204 to prevent the pin voltage from falling below the system logic low voltage 201 or rising above the system logic high voltage 202.
FIG. 2B illustrates the effect of an ideal clamp circuit on the real signal voltage 110 illustrated in FIG. 1. A perfectly clamped signal voltage 220 is produced. The ideal clamp circuit eliminates the undesirable voltage undershoot 111 and overshoot 112 by "clamping" the signal voltage to either the system logic high voltage 202 or system logic low voltage 201, as applicable. The ideal clamp circuit does not affect the signal voltage when it is within an acceptable operation region, i.e., between the system logic high voltage 202 and the system logic low voltage 201.
Actual prior art clamp circuits only approximate the ideal clamp circuit characteristic 200. Actual prior art clamp circuits all produce a qualitatively similar clamp current versus pin voltage characteristic 250 as illustrated in FIG. 2A. As seen in FIG. 2A, there are two areas in which actual prior art clamp circuits are non-ideal.
First, the pin voltages 251 and 252 at which prior art clamp circuits turn on are below and above, respectively, the pin voltages 201 and 202 at which the ideal clamp circuit turns on, typically by about 0.5-0.7 volts. These voltage differences 255 and 256 represent the clamp circuit "turn-on" voltages at which the clamp circuit switches from high impedance to low impedance.
Second, the low impedance state of the prior art clamp circuits exhibits a non-zero resistance. This variable resistance is equal to the slopes 253 and 254 of the clamp current versus pin voltage characteristic 250 when the pin voltage falls below, respectively, the system logic low voltage 201 by the amount of the turn-on voltage 255 or the system logic high voltage 202 by the amount of the turn-on voltage 256. The more quickly the slopes 253 and 254 become steep, the more closely the prior art clamp circuit approximates an ideal clamp circuit.
FIG. 2B illustrates the effect of an actual clamp circuit on the real signal voltage 110. A partially clamped signal voltage 221 is produced. The actual clamp circuit reduces, but does not eliminate, voltage undershoot 111 and voltage overshoot 112. Further, some signal ringing still remains as shown by the damped oscillations about both the system logic high voltage 121 and the system logic low voltage 120.
It is to be understood that the relationships between the unclamped, ideally clamped and actually clamped clamp current versus pin voltage characteristics shown in FIG. 2A and pin voltages shown in FIG. 2B are qualitatively, but not necessarily quantitatively accurate.
Prior art clamp circuits may be broadly classified into three groups: PN diode clamp circuits, Schottky diode clamp circuits, and grounded-gate MOS transistor clamp circuits.
A typical PN diode clamp circuit 310 is illustrated in FIG. 3A. The clamp circuit 310 has been used with both bipolar and CMOS integrated circuits for many years. The clamp circuit 310 utilizes the turn-on characteristics of PN diodes 311 and 312 to create the desired impedance characteristics. Diode 311 minimizes pin voltage overshoot and diode 312 minimizes pin voltage undershoot. The characteristics of PN diodes are well known and will be described here only as they apply to the characteristics of the clamp circuit 310.
The two PN diode parameters of interest are the diode forward turn-on voltage, V.sub.F, and the diode forward current, I.sub.F. V.sub.F is typically approximately 0.7 volts. In the clamp circuit 310, diode 311 has one terminal connected to the system supply voltage V.sub.CC (the system logic high voltage level) and the other terminal connected to the device pin voltage at node 315. Diode 312 has one terminal connected to the system ground voltage V.sub.SS (the system logic low voltage level) and the other terminal connected to the device pin voltage at node 315. Thus, for the clamp circuit 310, the turn-on voltage 252 shown in FIG. 2 is equal to V.sub.CC +V.sub.F and the turn-on voltage 251 is equal to V.sub.SS -V.sub.F.
The current-sourcing ability (i.e., clamp circuit impedance) of a PN diode is known to be exponentially related to the voltage across the diode. Thus, small changes in voltage across the diode produce a relatively large diode current (relatively small diode impedance). PN diode impedance is also a relatively weak function of the physical size of the diode (silicon area) on the integrated circuit chip, but this is typically not a substantial limitation in utilizing PN diode clamp circuits.
The clamp circuit 310 works well with bipolar integrated circuits, but has the undesirable operating characteristic of creating "minority carriers" which can induce latch-up in CMOS integrated circuits. When used with CMOS integrated circuits, the clamp circuit 310 requires very large areas of "guard ring" structures in order to minimize latch-up potential. The use of large guard-ring structures can have a significant adverse impact on the die size, and hence cost, of a CMOS integrated circuit.
A typical Schottky diode clamp circuit 320 is illustrated in FIG. 3B. Schottky diode 321 is placed between system supply voltage V.sub.CC and the device pin voltage at node 315, and Schottky diode 322 is placed between system ground voltage V.sub.SS and the device pin voltage at node 315.
The operation of the Schottky diode clamp circuit 320 is similar to that of the PN diode clamp circuit 310 with two exceptions: 1) Schottky diode forward turn-on voltage, V.sub.F, is typically approximately 0.5 volts (i.e., the Schottky diode is more ideal than the PN diode), and 2) Schottky diodes do not induce significant amounts of minority carriers (i.e., use of a Schottky diode clamp circuit 320 with CMOS integrated circuits would not require large guard-ring structures).
The clamp circuit 320 is widely utilized in bipolar integrated circuits because Schottky diodes are easily implemented in bipolar wafer fabrication processes. However, Schottky diodes are not easily implemented in CMOS wafer fabrication processes, so the use of the clamp circuit 320 in CMOS integrated circuits is very limited.
A typical grounded-gate transistor clamp circuit 330 comprising N-channel enhancement-mode MOS transistors 331 and 332 is illustrated in FIG. 3C. Transistor 331 is placed between system supply voltage V.sub.CC and the device pin voltage at node 315. The gate of transistor 331 is connected to the device pin voltage at node 315. Transistor 332 is placed between system ground voltage V.sub.SS and the device pin voltage at node 315. The gate of transistor 332 is connected to the system ground voltage V.sub.SS.
The clamp circuit 330 operates similarly to the previously described clamp circuits 310 and 320. The turn-on voltage V.sub.TN for modern N-channel MOS transistors is approximately 0.5-0.6 volts. The current-sourcing ability of a MOS transistor (i.e., the clamp current of clamp circuit 330) is given by the equation: ##EQU1## where V.sub.GS is the gate-to-source voltage of the transistor and .beta. is a transistor transconductance parameter that is given by the equation: ##EQU2## where .mu. and C.sub.OX are process dependent parameters, and W and L are design dependent parameters that represent the transistor width and length, respectively. As can be seen from equation (1), the clamp current for the clamp circuit 330 is quadratically related to V.sub.GS and linearly related to .beta.. For a given transistor design (i.e., .beta. fixed), the clamp current of the clamp circuit 330 is strictly a quadratic function of V.sub.GS.
The clamp circuit 330 has been widely utilized in CMOS integrated circuits because it does not require large guard-ring structures (as do PN diodes), and because it does not require complex processing steps (as do Schottky diodes or PN diodes). The primary disadvantage of the clamp circuit 330 is that, due to the weak quadratic dependence of transistor current on transistor gate-to-source voltage, the clamp circuit 330 may require very large physical transistors (large W/L ratio) in order to achieve satisfactorily low values of clamp circuit impedance.
Thus, in choosing a clamp circuit for a CMOS integrated circuit device, a tradeoff must be made between die size, latch-up sensitivity and wafer processing complexity.